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基于CMOS TSMC 0.25 μm工艺的2.4 GHz频率合成器

作者:王津,虞小鹏 日期:2008-11-03/span> 浏览:3515 查看PDF文档

基于CMOS TSMC 0.25 μm工艺的2.4 GHz频率合成器

王津,虞小鹏
(浙江大学 超大规模集成电路研究所,浙江 杭州 310027)

摘要:为了能满足2.4 GHz频段蓝牙无线通信标准,采用互补型金属氧化物半导体(CMOS) TSMC 025 μm工艺,设计了一个全集成的2.4 GHz工作频率的频率合成器。重点分析和设计了锁相环(PPL)中核心器件压控振荡器(VCO)和频率分频器两个高频电路,其中,压控振荡器采用交叉耦合的LC振荡器结构以减少相位噪声和面积,频率分频器采用增强型的移相技术,以提高工作频率和稳定性。实验数据表明,压控振荡器的相位噪声以及系统的锁定时间皆可满足2.4 G频段的无线通信需求。
关键词:蓝牙;互补型金属氧化物半导体;频率合成器;移相技术;锁相环;压控振荡器
中图分类号:TN386.1文献标识码:A文章编号:1001-4551(2008)10-0042-04

2.4 GHz frequency synthesizer based on TSMC 0.25 μm CMOS technology
WANG Jin, YU Xiao-peng
(Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China)
Abstract: To fulfill the Bluetooth communication standard, a 2.4 GHz fully integrated phase locked loop(PLL) based frequency synthesizer was designed in TSMC 0.25 μm complementary metal-oxide-semiconductor(CMOS) technology. As a key part of PLL, voltage controlled oscillator(VCO) and frequecy divider circuit was mainly analyzed and designed. To reduce phase noise and save silicon area, cross-coupled LC oscillator structure was used. To improve operating frenquency and stability of frequency divider, an enhanced phase switching technology was adopted. The experimental result shows that, the phase noise of VCO and the locking time of PLL can satisfy the requirement of wireless communication in 2.4 GHz range.
Key words: Bluetooth; complementary metal-oxide-semiconductor(CMOS); frequecy synthesizer;phase switching; phase locked loop(PLL); voltage controlled oscillator(VCO)
参考文献(References):
[1]HUNG C, FLOYD B, PARK N. Fully integrated 5.35 GHz CMOS VCO and prescalers[J]. IEEE Trans. Microwave Theory Tech.,2001,49(1):17-22.
[2]DULGER F, SINENCIO E S, BELLAOUAR A. Design Considerations in a BiCMOS Dual-modulus Prescaler[C]//IEEE Radio Frequency Integrated Circuits Symposium,2002:177-180.[3]CRANINCKX J, STEYAERT M. A 1.75 GHz/3 V dual-modulus divide by 128/129 prescaler in 0.7 mm CMOS[J]. IEEE Journal of Solid State Circuits,1996,31(7):890-897.
[4]KRISHNAPURA A, KINGET P. A 5.3 GHz programmable divider for HiperLAN in 0.25 μm CMOS[J]. IEEE Journal of Solid State Circuits,2000,35(7):1019-1024.
[5]KELIU S, SINENCIO E S, MARTINEZ J S, et al. A 2.4 GHz monolithic fractional-N frequency synthesizer with robust phase switching prescaler and loop capacitance multiplier[J]. IEEE Journal of Solid State Circuits,2003,38(6):866-874.
[6]RAZAVI B. Design of high speed, low power frequency dividers and phase-locked loops in deep submicron CMOS[J]. IEEE Journal of Solid State Circuits,1995,30(2):101-109.
[7]YU Xiao-peng. Fully Integrated CMOS Building Blocks for Phase Locked Loops in the Multi  GHz Range[D]. Singapore:Nanyang Technological University,2005.
[8]YUAN J, SVENSSON C. High speed CMOS circuit technique[J]. IEEE Journal of Solid State,1989,24(1):62-70.
[9]ROLAND E B. Phase Locked Loops Design,Simulation,and Applications[M].北京:清华大学出版社,2003.
[10]ALVAREZ J, SANCHEZ H, GEROSA G. A wide bandwidth low voltage PLL for power PCTM microprocessors[J]. IEEE Journal of Solid State Circuits,1995,30(4):383-391.



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